A) Field of the Invention
The present invention relates to a semiconductor photo detector, and more particularly to a semiconductor photo detector of the type that a MISFET (metal/insulator/semiconductor type field effect transistor) is connected to one terminal of a photodiode and the photodiode can be initialized by making MISFET conductive.
B) Description of the Related Art
CMOS type solid-state imaging devices have been proposed after the advent of CCD type solid-state imaging devices. Characteristic features of a CMOS type solid-state imaging device are a single power source, a low voltage drive and a low consumption power. Generally, CMOS type solid-state imaging devices are classified into the three-transistor type that one pixel is constituted of three transistors and one photodiode and the four-transistor type that one pixel is constituted of four transistors and one photodiode.
In a three-transistor type solid-state imaging device, one pixel includes a reset transistor, a source follower transistor and a select transistor. The reset transistor initializes the photodiode to a reset voltage. The source follower has the gate electrode connected to the photodiode and is controlled by voltage generated across the photodiode. The select transistor is serially connected to the source follower transistor to perform switching for reading a pixel signal. In a four-transistor type solid-state imaging device, a transfer transistor is inserted between a photodiode and the gate electrode of a source follower transistor, respectively of each pixel of a three-transistor type solid-state imaging device.
In the solid-state imaging device of either one of the three- and four-transistor types, when an image is to be taken, the reset transistor is first made conductive to initialize the n-type layer of the photodiode to a reference voltage (reset voltage). Thereafter, the photodiode receives light during a predetermined period. With this light reception, electrons are accumulated in the n-type layer of the photodiode and the n-type layer lowers its voltage. This voltage change is detected with the source follower transistor and output via the select transistor.
The voltage change of the n-type layer of the photodiode is dependent upon a junction capacitance of the photodiode. The smaller the junction capacitance, the larger the voltage changes. By reducing the junction capacitance of the photodiode, a photo detector sensitivity can be improved.
FIG. 14A is a cross sectional view of a photodiode and a reset transistor of a conventional CMOS type solid-state imaging device using an n+p-type photodiode. A field oxide film 201 is formed on the surface of a p-type silicon substrate 200, and defines active regions. The field oxide film 201 is disposed in a p-type well 205. An n-type layer 202 is formed in a partial surface layer of the active region. A partial outer periphery of the n-type layer 202 is in contact with the field oxide film 201. A p-type well 203 is formed in the active region where the n-type layer 202 is not formed. In this p-type well 203, an n-channel reset transistor 204 is formed.
The reset transistor 204 comprises: a source region 204S and a drain region 204D sandwiching a channel region; and a gate electrode 204G formed on a gate insulating film on the channel region. The source region 204S is in contact with the n-type layer 202. A reset voltage VR is applied to the drain region 204D of the reset transistor 204. The source region 204S is connected to the gate electrode of a source follower transistor.
A depletion layer extends under the n-type layer 202. As light enters from the upper surface of the silicon substrate 200 into the depletion layer via the n-type layer 202, pairs of electrons and holes are generated in the depletion region and electrons are accumulated in the n-type layer 202. In this manner, photoelectric conversion is achieved by light transmitted through the n-type layer 202. Since light of a shorter wavelength is likely to be absorbed in the n-type layer 202, the sensitivity for light of a shorter wavelength is lower than that for light of a longer wavelength.
As shown in FIG. 14B, as the n-type layer 202 is made thin, absorption of light of the shorter wavelength becomes small so that the sensitivity can be raised. However, as the n-type layer 202 is made thin, the depletion layer to be formed under the n-type layer 202 is likely to contact the shallow bottom area of the field oxide film 201 at the boundary P between the active region and nearby field oxide film 201. When the silicon substrate is subjected to local oxidation, stresses are concentrated upon this shallow bottom area of the field oxide film 201. Since the depletion layer contacts this shallow bottom area, leak current becomes large.
FIG. 15A is a cross sectional view of a photodiode and a reset transistor of a conventional CMOS type solid-state imaging device using a p+np-type photodiode, and FIG. 15B is a plan view thereof. A cross sectional view taken along one-dot chain line A15—A15 corresponds to FIG. 15A. Different points from the solid-state imaging device shown in FIG. 15A will be described.
A p+-type layer 210 is formed in a partial surface layer of an active region surrounded by a field oxide film 201, and an n-type layer 211 is formed under the p+-type layer. The n-type layer 211 is in contact with the source region 204S of a reset transistor 204. A depletion layer is formed at the interface between the n-type layer 211 and p+-type layer 210 and under the n-type layer 211. Since the n-type layer 211 is not exposed on the surface of the silicon substrate 200 but buried in the inside of the silicon substrate, the depletion layer does not contact the field oxide film 201. Leak current can therefore be made small.
In the CMOS type solid-state imaging device shown in FIGS. 15A and 15B, the depletion layer formed at the interface between the n-type layer 211 and p+-type layer 210 is thinner than the depletion layer formed under the n-type layer 211. Most of the junction capacitance is therefore the capacitance between the n-type layer 211 and p+-type layer 210. Since the junction capacitance becomes large, the photo detector sensitivity lowers. Since the depletion layer above the n-type layer 211 is large, photoelectric conversion is mainly achieved in the depletion layer formed under the depletion layer 211. Since light of a shorter wavelength attenuates when it transmits through the p+-type layer 210 and n-type layer 211, the sensitivity of the shorter wavelength among others lowers.
As shown in FIG. 15B, the outer periphery of the n-type layer 211 is spaced apart from the boundary between the field oxide film 201 and active region by a predetermined width toward the active region side, e.g., by 0.1 to 0.2 μm. It is therefore possible to prevent the depletion region to be formed at the interface between the n-type layer 211 and p+-type layer 210 from contacting the field oxide film 201. With this structure, however, the effective light reception area of the photodiode becomes small. As each pixel is made finer, the frame area between the n-type layer 211 and field oxide film 201 becomes large.